1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a test circuit to remedy a contact failure on a cell plate in a memory cell section.
2. Description of the Prior Art
FIG. 15 is a layout schematic diagram showing a conventional semiconductor integrated circuit, and FIG. 16 is a schematic cross-section taken along a Ixe2x80x94I line when the circuit of FIG. 15 is provided with a real device structure, and designates a DRAM hybrid system LSI. In FIGS. 15 and 16, reference numeral 10 designates a p-type semiconductor substrate; 11, 27 each designate a bit line; 12 designates an isolation region; 25 designates a p-well formed in the semiconductor substrate 10; 26 designates a transfer gate; 28a, 28b each designate a storage node; 29 designates a cell plate (hereinafter, abbreviated to as CP) on a memory cell region or MC region; 30 designates a contact constituted by titanium/tungsten (TiN/W) and the like; 31 designates an aluminum wiring; 35 designates a Vcp generation circuit which may generate a cell plate potential Vcp in response to a power supply potential Vcc from a main power supply; 51 designates a first interlayer dielectric; 52 designates a second interlayer dielectric; 53 designates a dielectric film such as silicon nitride and silicon oxide. The transfer gate 26 is typically formed with a silicide composed of a p-doped polycrystalline silicon film and a refractory metal, while the storage nodes 28a, 28b and cell plate 29 are typically formed with a p-doped polycrystalline silicon film.
Here, the storage nodes 28a, 28b are formed as a lower electrode of a capacitor on the first interlayer dielectric 51, to electrically connect with a lower transistor region. The dielectric film 53 for storing a capacitor capacitanceis formed on the storage nodes 28a, 28b, and the cell plate 29 is formed on the film 53 as an upper electrode of the capacitor. The aluminum wiring 31 externally connected is connected with the cell plate 29 via the contact 30 formed in the second interlayer dielectric 52. The vcp generation circuit 35 is connected to the aluminum wiring 31, and feeds a power supply to the cell plate 29 so that it may be maintained at the cell plate potential Vcp, while the bit line 27 is connected to a p-rich region or p+ region in the semiconductor substrate 10, and serves a fixation of the potential of the p-well.
FIG. 16 illustrates a structure assigned by 2 bits in a DRAM memory cell, and this structure serves as 1 bit by one pair of a transistor and a capacitor. Typically, a DRAM memory cell array is composed of a transistor and a capacitor, and the cell plate 29 as an upper electrode of the capacitor and the storage nodes 28a, 28b as lower electrodes thereof forms a stacked capacitor via the dielectric film 53 such as silicon nitride and silicon oxide to be inserted between the lower and upper electrodes. The structure of the stacked capacitor is specifically disclosed in JP-A 6-45553 and the like. The cell plate 29 is disposed to cover a memory cell block, and is typically connected with the upper aluminum wiring 31, which is connected with the main power supply (Vcc), via the contact 30 to be put under the potential fixation of the cell plate potential Vcp (=Vcc/2).
The operation will be next described.
The power supply potential Vcc is fed to the Vcp generation circuit 35 from the main power supply, and the cell plate potential Vcp generated herein is fed to the aluminum wiring 31 through the node CP. In addition, as described in FIG. 16, the cell plate potential Vcp is fed to the cell plate 29 via the contact 30, and a desired electric charge is stored in the capacitor constructed with the dielectric film between the storage nodes 28a, 28b. FIG. 16 illustrates a structure in which 2 bits are stored as storage information.
Since the conventional semiconductor integrated circuit is constituted as described above, in a DRAM hybrid system LSI with high integration developments of the circuit, it is required to reduce an annealing or thermal treatment which may be applied to such a device. This makes it difficult to manage the formations of fine patterns and holes and the electric characteristics of wiring resistances, contact resistances, and the like. In particular, the cell plate 29 of the CP electrode typically is formed with p-doped polycrystalline silicone, which makes it difficult to establish an ohmic characteristic of TiN/W adapted to the contact 30 section.
Further, it is also foreseen to cause a non-ohmic characteristic because of distributions in wafer processes. It is required to remedy such an electric characteristic failure by a test after completion of the wafer processes.
The present invention is implemented to solve the foregoing problems. It is therefor an object of the present invention to provide a semiconductor integrated circuit with a test circuit in which a circuit mounted on a semiconductor chip detects an abnormal contact resistance portion and then applies to this portion, thus recovering an ohmic characteristic of the corresponding contact portion, resulting in remedying a defective chip.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a memory cell including a field effect transistor formed in a semiconductor substrate, and a capacitor having a storage node connected to the source and a cell plate formed on the storage node via a dielectric film; a first wiring including the cell plate; a first power supply for feeding a first potential so as to maintain in a predetermined potential the cell plate of the capacitor; a second wiring having a first node and a second node connected to the first power supply; a first contact connected to the first wiring; a second contact connected to the first and second nodes; a logic circuit which may input a control signal externally at its first input and which connects its second input to the second input; a first switching circuit for selecting the first power supply or a second power supply for feeding a second potential higher than the first potential of the first power supply in response to an output after calculation in the logic circuit to feed either of the first and second potentials to the first node; a second switching circuit for selecting the first power supply or a third power supply for feeding a third potential lower than the first potential of the first power supply in response to an output after calculation in the logic circuit to feed either of the first and third potentials to the second node; and a third switching circuit for selecting a fourth power supply for feeding a fourth potential lower than the third potential, or a fifth power supply for feeding a fifth potential higher than the fourth potential and lower than the second potential in response to an output after calculation in the logic circuit to feed either of the fourth and fifth potentials to the semiconductor substrate associated with of the memory cell.
Here, the second and third potentials may be alternately applied to the first and second nodes of the second wiring.
In addition, a current limitation circuit may be connected to a wiring on the side of a third power supply of the second switching circuit, and an output from the current limitation circuit may be connected to the second input of the logic circuit.
In addition, the current limitation circuit may include a current mirror circuit and based on a wiring potential on the side of the third power supply of the second switching circuit, a main power supply for feeding a power supply potential or the third power supply for feeding the third potential may be selected to feed either of the power supply potential and the third potential to the second input of the logic circuit.
Further, a load may be connected to a wiring on the side of the main power supply, and the power supply potential may be fed to the second input of the logic circuit via the load.
Further, the logic circuit may serve as a control circuit for limiting the second and third potentials, which is fed to the cell plate constituting the capacitor, in response to a control signal.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, the circuit further including switching means, connected to the first and second wirings respectively, for feeding a high potential and a low potential alternately.
Here, the switching means may be connected to a transistor region of the semiconductor substrate, and feed the high and low potentials alternately.